1. Field of the Invention
The invention relates to a TFT electrode structure and its manufacturing method that can prevent metal diffusion to an adjacent dielectric layer during the fabrication of the TFT.
2. Description of the Related Art
FIGS. 1A˜1C show a TFT structure and its manufacturing method as disclosed in U.S. Pat. No. 6,218,221. The shown TFT structure has a multi-metal structure. As shown in FIG. 1A, a glass substrate 10 is used as a transparent insulating substrate. A conductive layer made of metal or a metallic alloy is formed on the glass substrate 10, and is etched to form a gate electrode 11 of the TFT, wherein the TFT is a multi-gate TFT structure. A dielectric layer 12 is formed over the glass substrate 10 and the gate electrode 11, and is used as insulating layer of the gate electrode 11. The dielectric layer 12 can be made of silicon oxide, silicon nitride, or a multi-layer combination of silicon oxide and silicon nitride. A semiconductor layer 13 made of amorphous silicon layer is formed on the dielectric layer 12, and a N+ doped amorphous silicon layer 14 is formed on the semiconductor layer 13.
As shown in FIG. 1B, a multi-metal structure 15 then is formed over the N+ amorphous silicon layer 14 and the dielectric layer 12. Each layer of the multi-metal structure 15 has a different etching resistance, the lower layer of greater etching resistance is used to prevent undesirable etching of the lower layer structure when the upper layer is etched.
FIG. 1C and 1D respectively show the structure of FIG. 1A and 1B being processed using a photo-mask 61 and different etching methods, to form desired patterned structures according to the actual demand.
Lastly, a passivation layer 17 is formed on the above structure by chemical vapor deposition, to isolate and protect the underlying layer structure. The passivation layer 17 can be made of silicon oxide or silicon nitride. A transparent conducting electrode 18 then is formed as pixel electrode by sputtering and a photo-mask method.
In the above method, a conductive layer 11 is formed on the glass substrate 10, and the deposition method used to form the dielectric layer 12 on the conductive layer 11 is performed under high temperature, which causes metal diffusion of the conductive layer 11. As a result, current leakage can occur through the dielectric layer 12.
FIG. 2A˜2E are schematic views illustrating a manufacturing method of a TFT array as disclosed in U.S. Pat. No. 5,838,037. In an embodiment of the U.S. Pat. No. 5,838,037 of a 3-electrode TFT structure, a gate electrode 22, a pixel electrode 23, and a counter electrode 24 as protective element are formed on substrate 21.
As shown in FIG. 2B, an insulating layer 25 is formed on the above 3 electrodes. A first amorphous silicon layer 26 and second amorphous silicon layer 27 are respectively formed and etched to have an adequate shape at a location above the gate electrode 22.
As shown in FIG. 2C, a contact hole 28 is etched through the insulating layer 25, so that the pixel electrode 23 electrically connects to the overlying electrode. As shown in FIG. 2D, source 29 and drain 30 are formed on the etched insulating layer 25 and amorphous silicon layers 26, 27, the pixel electrode 23 connecting to the drain 30. As shown in FIG. 2E, a passivation layer 31 is lastly formed as protective layer of the TFT.
Because the chemical vapor deposition used so far in the TFT manufacturing method is a high-temperature process, metallic ion can easily diffuse to the adjacent dielectric layer or other insulating layers. As a result, the manufacturing process is contaminated, which affects the TFT characteristics. Furthermore, the chemical vapor depositing machine can be affected by the environment, and the film quality formed can be easily affected by previously formed films.
In the conventional process, regardless of whether the transparent conducting electrode and the gate electrode are formed on or below the active layer, the dielectric layer or other insulating structures are usually formed by chemical vapor deposition after the gate formation is completed, which easily causes contamination of the chemical vapor depositing machine due to metallic ion diffusion.
The invention provides a method that can prevent metal diffusion and reduce the risk of metallic ion contamination in the chemical vapor deposition process. In the invention, the transparent pixel electrode is formed after the gate electrode metal so that the pixel transparent electrode can be used as a metallic ion barrier layer to prevent metal diffusion under high temperature from the gate electrode metal to adjacent insulating layers or the active layer. Further, the method used to form the transparent pixel electrode is physical vapor deposition process, which is affected less by the processing environment, and the transparent pixel electrode further is a conductive layer that is not affected by metal diffusion.